As for a semiconductor device such as a memory or the like, the more a semiconductor device is large-integrated and high-functioned, the more a test apparatus for testing the functions of the semiconductor device becomes expensive and the testing time becomes longer. An example of the test apparatus is a memory test system. To avoid the problem, a plurality of semiconductor devices (which are to be tested) are tested in parallel with one test apparatus.
FIG. 1 shows a schematic structure of a test system for performing parallel tests for a plurality of semiconductor devices. Devices to be tested (semiconductor devices) 900 shown in FIG. 1 include one semiconductor chip in one package. A test board 101 in FIG. 1 is provided with a plurality of sockets 102 and each of the sockets 102 is provided with a plurality of pins for connecting with a plurality of external terminals of the semiconductor devices. Each of the pins is connected with a measurement pin on a test apparatus 103 via a line on the test board 101 and a line 104 connecting between the test board 101 and the test apparatus 103. Because the number of the measurement pins on the test apparatus 103 is limited, the number of devices 900 that can be tested at one test procedure is limited to the number of the measurement pins on the test apparatus 103. Therefore, a test method is frequently utilized to increase the number of the devices to be tested at one test procedure.
FIG. 2 is an example of a test method to increase the number of semiconductor devices to be tested at one test procedure. FIG. 2 illustrates a schematic diagram of line connection for a packaged semiconductor device 900 mounted on the socket 102 on the test board. In FIG. 2, external terminals for control signals that are disposed on the semiconductor device 900 and connected to control signal pads (command, address and clock) of a semiconductor chip 911 in the semiconductor device 900 are connected with corresponding control signal measurement pins (driver pins) of the test apparatus via control lines 104B. As to DQ terminals that are disposed on the semiconductor device 900 and connected to data signal pads (DQ pads) on the semiconductor chip 911 in the semiconductor device 900, one of the plurality of DQ terminals is connected to a corresponding measurement pin of the test apparatus and the other DQ terminals are not connected to the test apparatus and in open state. The semiconductor device 900 shown in FIG. 2, only one degenerated data of a plurality of data, which should be output from a plurality of DQ terminals during a normal operation, is output from one DQ terminal to the test apparatus during a test operation. More concretely, when at least one test result among a plurality of test results (each corresponding to each DQ terminal) is a fail, the test result of a fail is output from a specified DQ terminal and when all of the test results are good, a good test result indicating a pass in the test is output from the specified DQ terminal. The number of semiconductors to be tested at one test procedure can be thus increased by reducing the number of DQ terminals on semiconductor devices connected to a test apparatus at a test procedure by such a way and therefore an efficiency of the test procedure for semiconductor devices can be improved.
Recently, a semiconductor device in which a plurality of semiconductor chips are packaged (multi-chips package, MCP) is being developed. FIGS. 3A and 3B show an examples of such a semiconductor device, in which two semiconductor chips 912 are integrated into one semiconductor package. FIG. 3A is a sectional drawing and FIG. 3B is a perspective view of it, respectively.
Patent Document 1 discloses a conventional test method for a multi-chip packaged semiconductor device containing a plurality of memory chips. According to the disclosure of Patent Document 1, data signals (TA0, TB0, TA1, TB1 and the like) of the plurality of memory chips are connected in common, and on the other hand, separate terminals are provided for control signals (/CE1 to /CE4). The data signal terminals of the memory chips are connected in common to a test apparatus and the control signal terminals are connected separately to the test apparatus. The connection shown in Patent Document 1 enables a read/write test only for memory chips selected by the control signals (/CE1 to /CE4) among the plurality of memory chips. Patent Document 1 discloses that an area for memory chip can be reduced by providing an input/output degenerating circuit in only a specified memory chip among the plurality of memory chips and read-testing other memory chips using the input/output degenerating circuit of the specified memory chip.